The present invention relates to a group IV element mixed crystal semiconductor, a fabrication method thereof, and a semiconductor device using such a mixed crystal semiconductor.
In recent years, attempts have been made to fabricate a semiconductor device utilizing heterojunction on a Si substrate for realizing a semiconductor device capable of operating at a higher speed than a conventional homojunction Si device. As materials for formation of heterojunction with Si, SiGe and SiGeC are expected promising, which are mixed crystal semiconductors including Ge and C, elements of the same group IV as Si.
In particular, a SiGeC ternary mixed crystal semiconductor has attracted considerable attention because the band gap and lattice constant thereof can be controlled independently by changing the mole fraction of the three elements, providing high degree of freedom in device design and allowing for lattice match with Si. For example, as disclosed in Japanese Laid-Open Patent Publication No. 10-116919, it is considered possible to realize a field effect transistor capable of operating at a higher speed than a conventional Si device by utilizing conduction band discontinuity formed at a hetero-interface between a Si layer and a SiGeC layer to use two-dimensional electron gas generated at the interface as a carrier.
Presently, a SiGeC mixed crystal is prepared by a method in which C source gas is introduced during epitaxial growth of a SiGe layer, or a method in which C ions are implanted into a SiGe layer.
However, as described in Applied Physics Letters, Vol. 65 (1994) p. 2559, for example, the incorporation of carbon into a SiGe layer has its limitation. It is known that the SiGe layer markedly degrades in crystalline quality and becomes amorphous when about 4% or more of C atoms is introduced into the SiGe layer. Moreover, according to experiments carried out by the present inventors, a SiGeC layer degrades in crystalline quality when it is annealed at certain temperatures. In particular, it has been observed that the degradation in crystalline quality tends to become more significant as the C concentration increases.
FIG. 8 is a view of data obtained from the experiments carried out by the present inventors, showing a change in X-ray diffraction spectra of samples of a SiGe0.31C0.0012 crystal layer annealed at various temperatures. As is observed from this figure, the positions of the diffraction peaks of the samples annealed at temperatures of 800xc2x0 C. or lower are hardly different from that of the as-grown sample. However, the position of the diffraction peak of the sample annealed at 900xc2x0 C. exhibits a little shift from that of the as-grown sample, and as the annealing temperature is increased to 950xc2x0 C. or higher, the position of the diffraction peak of the annealed sample starts shifting widely from that of the as-grown sample. Moreover, for the samples annealed at temperatures of 1000xc2x0 C. or higher, while the half-width at the peak increases, fringes observed in the diffraction spectrum of the as-grown sample almost disappear. Thus, according to the illustrated experiment data, it is found that the SiGe0.31C0.0012 crystal layer degrades in crystalline quality when it is annealed at about 950xc2x0 C. or higher.
The present inventors have further carried out experiments to investigate the cause of the degradation in the crystalline quality of the SiGeC crystal layer, and found that the degradation of the SiGeC crystal layer by annealing is mainly because Gexe2x80x94C bonds in the mixed crystal is markedly unstable compared with Sixe2x80x94C bonds.
FIGS. 7(a) and 7(b) are views showing changes in X-ray diffraction spectra of samples of a Ge0.98C0.02 crystal layer grown on a Ge substrate and a Si0.98C0.02 crystal layer grown on a Si substrate, respectively, annealed at various temperatures. The Ge0.98C0.02 crystal layer was grown by implanting C ions into a Ge substrate followed by annealing, and the Si0.98C0.02 crystal layer was epitaxially grown on a Si substrate using Si and C source gases.
As shown in FIG. 7(a) where a Ge0.98C0.02 crystal layer was grown on a Ge substrate, the diffraction peaks of the samples annealed at 475 to 550xc2x0 C. are observed at substantially the same positions, whereas no diffraction peaks are observed for the samples annealed at 450xc2x0 C. or lower. When the annealing temperature is 600xc2x0 C. or higher, the diffraction peak position of the Ge0.98C0.02 crystal layer shifts. In particular, the peak disappears for the sample annealed at 700xc2x0 C. or higher. This indicates that the GeC crystal is subjected to some change when it is annealed at a temperature of 600xc2x0 C. or higher. More specifically, it indicates that Gexe2x80x94C bonds are segregated.
As shown in FIG. 7(b) where a Si0.98C0.02 crystal layer was grown on a Si substrate, the diffraction peak is clearly observed for the Si0.98C0.02 crystal layer annealed at a temperature up to 1000xc2x0 C.
In view of the above results, it is found that the instability of Gexe2x80x94C bonds is a cause of the degradation in the crystalline quality of the SiGeC crystal, indicating that suppressing formation of Gexe2x80x94C bonds is a decisive factor for improving the crystalline quality.
An object of the present invention is providing a SiGeC mixed crystal with good crystalline quality and thermal stability, a fabrication method thereof, and a semiconductor device using such a SiGeC mixed crystal. This can be achieved by eliminating the cause of instability of a SiGeC layer, i.e., by forming a short-period superlattice layer which is free from Gexe2x80x94C bonds but nevertheless can be considered as a SiGeC crystal layer.
The semiconductor crystal of the present invention comprises a Si1xe2x88x92xGex/Si1xe2x88x92yCy superlattice structure (0 less than x,y less than 1) including two or more periods of alternately grown Si1xe2x88x92xGex layers containing Si and Ge as major components and Si1xe2x88x92yCy layers containing Si and C as major components, wherein the Si1xe2x88x92xGex/Si1xe2x88x92yCy superlattice structure functions as a single SiGeC layer.
The above Si1xe2x88x92xGex/Si1xe2x88x92yCy superlattice structure can function as a single SiGeC layer with Gexe2x80x94C bonds hardly contained therein. As a result, a semiconductor crystal which can maintain good crystalline quality stably even when subjected to annealing and still has the same function as a SiGeC layer is obtained.
The thickness of each of the Si1xe2x88x92xGex layers and the Si1xe2x88x92yCy layers in the Si1xe2x88x92xGex/Si1xe2x88x92yCy superlattice is smaller than the thickness which allows discrete quantization levels to be generated. This ensures to obtain the Si1xe2x88x92xGex/Si1xe2x88x92yCy short-period superlattice which functions as a single SiGeC layer.
The semiconductor device of the present invention comprises: a substrate; a first semiconductor layer containing at least Si, formed on the substrate; and a second semiconductor layer formed in contact with the first semiconductor layer for functioning as a SiGeC layer, wherein the second semiconductor layer has a structure including two or more periods of alternately grown Si1xe2x88x92xGex layers (0 less than x less than 1) containing Si and Ge as major components and Si1xe2x88x92yCy layers (0 less than y less than 1) containing Si and C as major components.
By the above construction, heterojunction such as Si/SiGeC can be formed between the first and second semiconductor layers. Utilizing this heterojunction, an advanced semiconductor device, e.g., a field effect transistor which functions as a high electron mobility transistor (HEMT), can be provided.
The thickness of each of the Si1xe2x88x92xGex layers and the Si1xe2x88x92yCy layers is preferably smaller than the thickness which allows discrete quantization levels to be generated.
The first fabrication method of a semiconductor crystal of the present invention comprises repeating epitaxial growth of a Si1xe2x88x92xGex layer (0 less than x less than 1) containing Si and Ge as major components and epitaxial growth of a Si1xe2x88x92yCy layer (0 less than y less than 1) containing Si and C as major components alternately by two or more times, to form a Si1xe2x88x92xGex/Si1xe2x88x92yCy short-period superlattice which functions as a single SiGeC layer.
By the above method, the semiconductor crystal described above can be easily fabricated.
The second fabrication method of a semiconductor crystal of the present invention comprises the steps of: (a) repeating epitaxial growth of a Si1xe2x88x92xGex layer (0 less than x less than 1) containing Si and Ge as major components and epitaxial growth of a Si layer containing Si as a major component alternately by two or more times, to form a Si1xe2x88x92xGex/Si multilayer structure; (b) implanting C ions into the Si1xe2x88x92xGex/Si multilayer structure; and (c) annealing the C-implanted Si1xe2x88x92xGex/Si multilayer structure, to form a Si1xe2x88x92xGex/Si1xe2x88x92yCy multilayer structure (0 less than y less than 1).
According to the above method, the phenomenon of migration of C atoms to the Si layers caused by segregation of Gexe2x80x94C bonds during the annealing is utilized. Also, the substrate surface can be kept clean since no source gas for C doping is required during epitaxial growth of the layers. Thus, a Si1xe2x88x92xGex/Si1xe2x88x92yCy multilayer structure which can be used for a variety of applications is obtained.
In the step (a), the Si1xe2x88x92xGex layers and the Si layers may be formed so that the Si1xe2x88x92xGex layers and Si1xe2x88x92yCy layers of the resultant Si1xe2x88x92xGex/Si1xe2x88x92yCy multilayer structure have a thickness large enough to allow discrete quantization levels to be generated. In this case, a Si1xe2x88x92xGex/Si1xe2x88x92yCy multilayer structure which functions as a multiquantum barrier (MQB) or the like useful for construction of a quantum device is obtained.
Alternatively, in the step (a), the Si1xe2x88x92xGex layers and the Si layers may be formed so that the Si1xe2x88x92xGex layers and Si1xe2x88x92yCy layers of the resultant Si1xe2x88x92xGex/Si1xe2x88x92yCy multilayer structure have a thickness smaller than the thickness which allows discrete quantization levels to be generated. In this case, a Si1xe2x88x92xGex/Si1xe2x88x92yCy multilayer structure which functions as a single SiGeC layer useful for construction of a heterojunction semiconductor device is obtained.
In the above fabrication method, the annealing temperature in the step (c) is preferably higher than 700xc2x0 C.